Field of the Invention
The invention relates to electronic circuit, and particularly relates to an integrated circuit and an operation method of a serializer/deserializer (SERDES) physical (PHY) layer circuit.
Description of Related Art
Serializer/deserializer (which is generally referred to as SERDES) may transform parallel data into serial data, or transform serial data into parallel data. FIG. 1 is a block schematic diagram of integrated circuit configured with general SERDES. Referring to FIG. 1, the integrated circuit 100 includes an upper layer circuit 110 and a plurality of SERDES physical layer (PHY layer) circuits. For example, n SERDES PHY layer circuits 120_1, 120_2, . . . , 120_n are illustrated in FIG. 1, where n is any integer determined according to an actual design requirement.
The upper layer circuit 110 can be a data link layer, a network layer and/or other functional circuit. The SERDES PHY layer circuits 120_1-120_n respectively have a data pin. The data pins of the SERDES PHY layer circuits 120_1-120_n are electrically coupled to the upper layer circuit 110. The SERDES PHY layer circuits 120_1-120_n may transform parallel data output from the upper layer circuit 110 into serial data, and output the serial data to a circuit outside the integrated circuit 100 through data pads 130_1, 130_2, . . . 130_n; and/or receive serial data from the circuit outside the integrated circuit 100 through the data pads 130_1-130_n, and transform the serial data into parallel data for providing to the upper layer circuit 110.
The SERDES PHY layer circuits 120_1-120_n respectively have a reference resistor pin. The reference resistor pins of the SERDES PHY layer circuits 120_1-120_n are electrically connected to reference resistor pads 140_1, 140_2, . . . , 140_n. The reference resistor pads 140_1-140_n are respectively connected to reference resistors 10_1, 10_2, . . . , 10_n. During an initialization period after power is supplied to the SERDES PHY layer circuits 120_1-120_n, the SERDES PHY layer circuits 120_1-120_n may simultaneously enter a calibration state, such that the SERDES PHY layer circuits 120_1-120_n respectively perform current calibration by using the reference resistors 10_1-10_n electrically connected to the reference resistor pads 140_1-140_n. In case that a reference voltage is supplied to the reference resistors 10_1-10_n, the reference resistors 10_1-10_n may respectively provide corresponding reference currents to the SERDES PHY layer circuits 120_1-120_n, and the SERDES PHY layer circuits 120_1-120_n may respectively perform the current calibration according to the reference currents.
Generally, resistances of the reference resistors 10_1-10_n are the same. If the SERDES PHY layer circuits 120_1-120_n may commonly use a single reference resistor, the amount of the reference resistors 10_1-10_n can be greatly decreased. However, the SERDES PHY layer circuits 10_1-120_n cannot commonly use a same reference resistor since the SERDES P layer circuits 120_1-120_n may simultaneously enter the calibration state (i.e. simultaneously use the same reference resistor). When the SERDES PHY layer circuits 120_1-120_n simultaneously use the same reference resistor, the reference current required for the current calibration is changed due to a parallel effect, which influences a result of the current calibration.